Reducing stress in integrated circuits

ABSTRACT

A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.

BACKGROUND OF INVENTION

[0001]FIG. 1 shows an integrated circuit chip 101. The chip comprises anIC 130 formed on a surface of a substrate 110. The IC comprises variouscomponents, such as transistors, resistors and capacitors. Thecomponents are interconnected to create the desired functions. One ormore passivation layers can be provided over the components forprotection from, for example, moisture.

[0002] Ferroelectric metal oxide ceramic materials such as leadzirconate titanate (PZT) or strontium bismuth tantalate (SBT) are usedto form certain components, such as capacitors. The capacitors can beused to form ferroelectric memory cells. A ferroelectric memory cellstores information in the capacitor as remanent polarization. The logicvalue stored in the memory cell depends on the polarization of theferroelectric capacitor. To change the polarization of the capacitor, avoltage which is greater than the switching voltage (coercive voltage)needs to be applied across its electrodes. An advantage of theferroelectric memory cell is that it retains its polarization stateafter power is removed, resulting in a non-volatile memory cell.

[0003] The various materials of the IC, after processing, may produce anoverall stress (referred to as remaining stress). The remaining stress,for example, can be tensile stress (e.g., expansive). Such remainingstress can create bowing in the substrate on which the IC is formed, asshown in FIG. 2. However, some components, such as ferroelectriccapacitors, have been found to be very sensitive to mechanical stress.For example, local stress in the ferroelectric devices has been found toadversely impact device performance and reliability.

[0004] From the foregoing discussion, it is desirable to provide an ICwhich avoids the adverse impact of stress resulting from processing.

SUMMARY OF INVENTION

[0005] The invention relates to semiconductor processing. In particular,the invention relates to compensating for stress on a substrateresulting from semiconductor processing. In one embodiment, asemiconductor chip comprising an IC formed on a first surface of asubstrate. The IC produces a remaining stress of a first type on thesubstrate. On a second surface of the substrate, a stress compensatinglayer is provided. The stress compensating layer produces a stress of asecond type, which is opposite of the remaining stress. As a result, thestress compensating layer reduces the effective stress on theferroelectric device, thus compensating for stress which can adverselyaffect performance and reliability.

[0006] In one embodiment, the stress compensating layer comprises adielectric layer. The dielectric layer preferably comprises siliconnitride or silicon oxide. In a preferred embodiment, the dielectricmaterial is deposited using plasma enhanced CVD. Such techniquesadvantageously enable the stress compensating layer to be tuned withspecific stress characteristics.

BRIEF DESCRIPTION OF DRAWINGS

[0007] FIGS. 1-2 show an integrated circuit and affects of mechanicalstress;

[0008]FIG. 3 shows an integrated circuit in accordance with oneembodiment of the invention; and

[0009]FIG. 4 shows a process flow of forming an IC in accordance withone embodiment of the invention.

DETAILED DESCRIPTION

[0010] The invention relates generally to the fabrication of ICs.Generally, a plurality of ICs are formed on a semiconductor substrate,such as a silicon wafer, simultaneously. The sequence of process stepsof forming the components on the wafer, including depositing the finalpassivation over the components, is referred to as the front-endprocess. After the front-end process is finished, the wafer is diced toseparate the ICs into individual chips. The chips are then packaged,resulting in a final product that is used in, for example, consumerproducts such as computer systems, cellular phones, personal digitalassistants (PDAs), and other electronic products. In particular, theinvention relates to reducing stress in ICs that can adversely impactperformance and reliability.

[0011]FIG. 3 shows a semiconductor chip 301 in accordance with oneembodiment of the invention. As shown, the chip comprises a substrate310. The substrate, for example, is a semiconductor wafer comprisingsilicon. Other types of substrates can also be useful. An IC 330 isformed on a first (top) surface of the substrate.

[0012] In one embodiment, the IC comprises ferroelectric components,such as memory cells. The memory cells, for example, are interconnectedto form a memory array. The cells of the memory array can be arranged invarious types of architectures, such as open or folded. Other types ofarchitectures, such as series architectures, are also useful. Seriesarchitectures are described in, for example, US patent titled“Semiconductor Memory Device and Various Systems Mounting Them”, U.S.Pat. No. 5,903,492, filed on Jun. 10, 1997, which is herein incorporatedby reference for all purposes. In one embodiment, the memory array alongwith controlling or support circuitry forms a memory IC. Forming othertypes of ICs is also useful.

[0013] As previously discussed the front-end process results indepositing various layers on the substrate to form the IC. The front-endprocess can produce a remaining stress, which can create local stress onthe device. This can adversely impact device performance. Additionally,the remaining stress can cause the substrate to bow. The substrate wouldbow to form a concave shape in the presence of compressive stress orconvex shape in the presence of tensile stress. The greater the amountof stress, the more the substrate would bow. The amount of remainingstress can easily be measured using, for example, optical techniques.Such techniques are described in, for example, Milton Ohring, “TheMaterials Science of Thin Films, Academic Press, Inc., Boston 1991,which is herein incorporated by reference for all purposes.

[0014] In accordance with the invention, a stress compensating layer 370is provided on the second (bottom) surface of the substrate. The stresscompensating layer, in one embodiment, creates a stress (compensatingstress) which is opposite of the remaining stress. The compensatingstress offsets the effects of the remaining stress, thus reducing bowingof the substrate.

[0015] In a preferred embodiment, the stress compensating layerintroduces a compensating stress which is substantially equal to aboutthat of the remaining stress. For example, if the remaining stressproduced by the front end process is about 5×10 mPa of tensile stress,the stress compensating layer would be selected to cause about the samemagnitude of compressive stress. More preferably, the stresscompensating layer produces a compensating stress which also takes intoaccount of the stress later introduced by the package. Depending on thetype of stress created by the package relative to that of the remainingstress, the compensating stress could be increased or decreased. Forexample, if the package and remaining stress are of the same type (e.g.,tensile), the compensating stress would be increased to accommodate forthe added stress. On the other hand, if the stresses are of the oppositetype, then the compensating stress would be reduced by about an amountequal to the package stress.

[0016] In one embodiment, the stress compensating layer comprises adielectric material as the compensating layer. Other types of dielectricor non-dielectric materials can also be used. For example, conductivematerials such as metals could be used. The stress which the stresscompensating layer produces depends on the material used and/or itsthickness. Various techniques can be used to form the stresscompensating layer, depending on the material used. For example,dielectric materials can be deposited by chemical vapor deposition (CVD)while metal by sputtering.

[0017] In a preferred embodiment, the stress compensation layercomprises a dielectric material such as silicon nitride or oxide. Thedielectric material is preferably deposited by plasma-enhanced CVD(PECVD). Plasma-enhanced CVD is preferred since such techniquesadvantageously enables the dielectric material to be deposited with thedesired stress characteristics (e.g., tunable). For example, thedielectric layer can be tuned to have the desired stress orientation(e.g., compressive or tensile). The magnitude of the stress can bedetermined by, for example, the thickness of the stress compensatinglayer.

[0018]FIG. 4 shows a process flow 403 for forming an integrated circuitin accordance with one embodiment of the invention. Typically, aplurality of ICs are fabricated on a semiconductor wafer in parallel.Various types of ICs can be fabricated. In one embodiment, ferroelectricmemory ICs are fabricated on the wafer. Fabricating other types of ICsis also useful. The front-end process of a ferroelectric memory ICcomprises, for example, ferroelectric memory cell (transistor andcapacitors), support circuitry, and metallization modules. After thefront-end process is completed at step 415, the wafer is tested andsorted at step 425.

[0019] In general, the wafer is processed with a thickness which isgreater than necessary to facilitate processing and handling. In suchcase, the backside of the wafer may be grinded to reduce its thicknessafter testing and sorting. Backgrinding the wafer prior to testing andsorting is also useful. By reducing the thickness of the wafer, the overthickness of the final packaged chip can be reduced. In one embodiment,the stress on the wafer from front end processing is performed at step435 to determine the stress on the wafer. If no backgrinding isperformed, the stress on the wafer can be measured after front-endprocessing or testing.

[0020] Once the stress is determined, a stress compensation layer inaccordance with the invention is formed on the backside of the wafer.The stress compensation layer introduces a compensating stress on thewafer. The compensating stress reduces, for example, local stress on theIC. In another embodiment, the compensating stress also takes intoaccount of the stress asserted by the subsequent package. Afterformation of the stress compensation layer, the wafer is diced,separating the ICs into chips. The chips are then packaged at step 465.The packaged ICs are tested for defects at step 475.

[0021] In other embodiments, the stress compensation layer can be formedon the substrate during other parts of the process flow. The stresscompensation layer can be formed on the backside of the substrate at anypoint in the process prior to packaging. Preferably, the stresscompensation layer is formed prior to dicing the wafer. This isparticularly useful for process flows which do not involve grinding theback of the wafer or providing protective layer on the backside of thewafer to protect against cross-contamination of tools or contaminationof the wafer.

[0022] The stress induced on the wafer can be measured, for example,after front-end processing. The result of the measurement can be appliedas a general rule to fabricating a specific type of IC. The stress fromthe package can also be taking into consideration when determining thecompensating stress. Since the package is formed at the final process,it can be estimated or actually measured. For actual measurements, itmay be useful to sample a large population and take the mean value asthe measured value.

[0023] In another embodiment, a stress compensation layer is providedfor a specific wafer. In such case, the remaining stress on the wafer ismeasured after front-end processing. The stress compensation layer isselected or tuned to produce a compensating stress to offset themeasured stress value. Preferably, the stress compensation layer alsofactors in the stress from the package. The application of stresscompensation layer to compensate for remaining stress of a specificwafer can be facilitated by deposition techniques which can tune thestress characteristics.

[0024] While the invention has been particularly shown and describedwith reference to various embodiments, it will be recognized by thoseskilled in the art that modifications and changes may be made to thepresent invention without departing from the spirit and scope thereof.The scope of the invention should therefore be determined not withreference to the above description but with reference to the appendedclaims along with their full scope of equivalents.

1. An semiconductor chip comprising: a substrate; an integrated circuit(IC) formed on a first surface of the substrate, the IC producing aremaining stress of a first type on the substrate; and a stresscompensating layer located on a second surface of the substrate which isopposite the first surface, the stress compensating layer producing acompensating stress of a second type, the second type being opposite ofthe first type, the compensating stress reducing an overall stress onthe substrate to reduce bowing.
 2. The semiconductor chip of claim 1wherein the IC comprises ferroelectric components.
 3. The semiconductorchip of claim 2 wherein the ferroelectric components are ferroelectricmemory cells interconnected to form a memory array.
 4. The semiconductorchip of claim 3 wherein the ferroelectric components are memory cellsarranged in a open, folded, or series architecture.
 5. The semiconductorchip of claim 1 wherein IC comprises memory cells.
 6. The semiconductorchip of claim 1 wherein IC comprises memory cells arranged in a open,folded, or series architecture.
 7. The semiconductor chip of claim 1wherein the IC comprises components which are sensitive to stress. 8.The semiconductor chip of claim 1 wherein the compensating stress issubstantially equal to about the remaining stress.
 9. The semiconductorchip of claim 8 wherein the compensating stress is substantially equalto about the remaining stress and chip package stress.
 10. Thesemiconductor chip of claim 9 wherein the compensation layer comprises adielectric material.
 11. The semiconductor chip of claim 10 wherein thedielectric layer can be tuned with specific stress characteristics. 12.The semiconductor chip of claim 11 wherein the dielectric layer isdeposited by plasma-CVD techniques.
 13. The semiconductor chip of claim10 wherein the dielectric material comprises silicon nitride or siliconoxide.
 14. The semiconductor chip of claim 13 wherein the dielectriclayer is deposited by plasma-CVD techniques.
 15. The semiconductor chipof claim 13 wherein the dielectric layer can be tuned with specificstress characteristics.
 16. The semiconductor chip of claim 15 whereinthe dielectric layer is deposited by plasma-CVD techniques.
 17. Thesemiconductor chip of claim 10 wherein the dielectric layer is depositedby plasma-CVD techniques.
 18. The semiconductor chip of claim 8 whereinthe compensation layer comprises a dielectric material.
 19. Thesemiconductor chip of claim 18 wherein the dielectric layer can be tunedwith specific stress characteristics.
 20. The semiconductor chip ofclaim 19 wherein the dielectric layer is deposited by plasma-CVDtechniques.
 21. The semiconductor chip of claim 18 wherein thedielectric material comprises silicon nitride or silicon oxide.
 22. Thesemiconductor chip of claim 21 wherein the dielectric layer is depositedby plasma-CVD techniques.
 23. The semiconductor chip of claim 21 whereinthe dielectric layer can be tuned with specific stress characteristics.24. The semiconductor chip of claim 23 wherein the dielectric layer isdeposited by plasma-CVD techniques.
 25. The semiconductor chip of claim18 wherein the dielectric layer is deposited by plasma-CVD techniques.26. A method of fabricating an IC comprising: performing front-endprocesses on a substrate to form an IC on a first surface of asemiconductor substrate; measuring the remaining stress on the substratecaused by the front-end processes; forming a stress compensating layeron a second surface of the substrate, the stress compensating layerproducing a compensating stress of an opposite type from the remainingstress to reduce performance degradation due to local stress.